Publication

Competitive-learning-based spiking neural networks are capable of rapid, highly accurate pattern recognition with minimal data through denoising mechanisms provide by adaptive interneuron inhibition. However, hardware implementations of such networks are currently area-inefficient due to the high device count require to execute dual excitatory-inhibitory synapses. To mitigate this, n-/p- reconfigurable tungsten diselenide memtransistors is introduced that can execute excitatory and inhibitory synapses in a highly compact bio-inspired feature extractor hardware architecture. The reconfigurability is realized through a dual mode memory device with a flash-memory-like floating-gate for n-/p- programing and a memristor-like selenium vacancy-based resistive switching that varies in memristive output with majority carrier modulation. Through a device-system codesign, an effective 27% device count reduction in the peripheral circuits is achieved , which ameliorates circuit component congestion and circuit complexity. Compared to the prevalent winner-takes-all approach, the proposed machine learning with adaptive interneuron inhibition achieves high-accuracy convergence with up to five times smaller training dataset. This accelerated learning can potentially enable edge-artificial intelligence (AI) processors capable of ultra-low-energy training with limited data.

Researcher/Author:  Jin Feng Leong, Zihang Fang, Maheswari Sivan, Jieming Pan, Baoshan Tang,
Evgeny Zamburg, and Aaron V-Y Thean

Published in:  Advanced Functional Materials

To download the paper, please 

proceed to:  https://doi.org/10.1002/adfm.202302949