Publication

A 12-bit hybrid SAR ADC with SAR search assisted by comparator offset injection is presented. The proposed ADC architecture reuses offset calibration circuitry for conversion of the last two LSBs, reducing the required capacitive DAC resolution and pushing its total capacitance down to its thermal noise limit. The proposed ADC can be calibrated without requiring any accurate input generation. The prototype ADC, fabricated in 40nm CMOS, occupying an active core area of 0.0315mm2 , and operating at 0.35-0.45V for sampling rates ranging from 0.4 to 80 kS/s respectively, achieves the lowest Walden-FOM between 0.425-0.947fJ/conv-step, with an SNDR > 64.7dB and SFDR > 74.3dB.

Researcher/Author:  

Japesh Vohra, Karim Ali Ahmed & Massimo Alioto

Published in:

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)

To download the paper, please proceed to:  

10.1109/ESSCIRC59616.2023.10268816