Researcher

Jayasanker Jayabalan received B.Eng (Hons.) in Electronics and Communication Engineering from Madurai Kamaraj University and M.Sc, Ph.D. degrees in Electrical and Computer engineering from National University of Singapore. He is a Research Fellow with the National University of Singapore where he focuses on Machine Learning Guided Test and Failure Analysis & Diagnostic Capability Development for Next Generation 3D-IC Packaging Technologies. He possesses over 25 years of industry and research experience in Semiconductor Test Technology. He was a Principal Design Engineer with Avago Technologies, leading Design-for-Test (DfT) development for several of Avago’s Networking ASIC products and thereafter a Research Scientist with IME, leading 2.5D System-In-Package DfT activities. He started his career with National Semiconductors, Singapore, where he was a Test Engineer for NS’s communication and computing products.