A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500um2, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm
November 5, 2023
Publication
- A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500um2, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm
- November 5, 2023
Current references are fundamental building blocks in sensor interfaces and other analog circuitries [1]–[9]. In applications with low-cost targets, their area and testing effort need to be minimized, and trimming must be eliminated. In power-constrained systems, their net power (i.e., not going into their output bias current IREF) and minimum supply voltage Vmin need to be kept low, so as to minimize the power burden and remove supply scaling limitations at the system level. Unfortunately, lower net power generally leads to poorer accuracy due to PVT variations, requiring innovation to make the power-accuracy tradeoff more favorable while avoiding trimming.
Researcher/Author:
Luigi Fassio, Hoang Hong Hanh, Massimo Alioto
Published in:
2023 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Date Added to IEEE Xplore: 18 December 2023
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