SHINE Overseas Speaker Series Workshop on “Future Directions for Moore’s Law and Advanced Packaging
October 29, 2024
SHINE Overseas Speaker Series Workshop: Future Directions for Moore’s Law and Advanced Packaging | 29 Oct 2024
On 29 October 2024, SHINE held an insightful Overseas Speaker Series Workshop featuring Dr. Valluri (Bob) Rao, a renowned independent consultant, former Intel Fellow and IEEE Fellow. Dr. Rao’s presentation, “Future Directions for Moore’s Law and Advanced Packaging,” explored the urgent challenges and technological innovations needed to support the future demands of semiconductor scaling, particularly in the era of Artificial Intelligence (AI) and Large Language Models (LLMs).
Key Takeaways
The presentation highlighted the growing impact of LLMs on the demand for high-performance computing power. As AI applications continue to expand, millions of interconnected GPUs are required to meet processing demands. Dr. Rao noted that the power consumption for such systems is approaching levels that may soon require energy equivalent to multiple nuclear reactors. This rapid growth has led to a renewed focus on advanced packaging, monolithic 3D processing, and heterogeneous integration as critical enablers for performance scaling.
- Energy and Processing Challenges: Approximately 50% of power in these systems is dissipated by compute chips, an area that Moore’s Law alone cannot continue to address. Advanced packaging and photonics are essential to handle the high energy demands and data movement challenges between compute and memory chips. Dr. Rao proposed developing innovative approaches for monolithic 3D post-processing and advanced packaging solutions to meet these demands.
- Technological Innovations Enabling Moore’s Law Scaling: Dr. Rao emphasized that many advanced technologies, including EUV, nanoimprint, multi-patterning, and monolithic 3D, are crucial for scaling Moore’s Law through 2037 and beyond. New developments in multi e-beam mask writers with 500K beams, as well as computers optimized for advanced lithography, are paving the way for these innovations.
- Stacked Nanosheet Transistors and Defect Management: Stacked nanosheet transistors are expected to be the workhorse for future chip designs. Dr. Rao discussed the importance of integrating these new device concepts with advanced packaging methods such as Stanford’s N3XT 3D Mosaic. Furthermore, he highlighted that addressing defect, yield, reliability, and metrology issues is essential to sustaining Moore’s Law, as these factors will impact the feasibility of next-generation semiconductor technologies.
- Cooled CMOS and Heterogeneous Integration: Cooled CMOS presents a promising opportunity, provided effective thermal solutions can be developed. Heterogeneous integration and the use of chiplets enable higher yields and reduced costs by interconnecting smaller die on a single substrate. This integration also allows for the inclusion of novel devices that are otherwise difficult to incorporate directly onto silicon.
Dr. Rao’s presentation underscored the importance of co-developing advanced packaging and 3D post-processing technologies to meet the growing demands of the AI-driven era.
The workshop provided attendees with a comprehensive perspective on the critical innovations needed to sustain semiconductor scaling and support future AI applications.
Looking Forward
The session concluded with a discussion on the role of rapid prototyping, nano-imprint, and optical patterning technologies in enabling experimental ideas and accelerating development in the semiconductor industry.
Dr. Rao’s insights resonated strongly with the audience, providing valuable guidance for those involved in advancing Moore’s Law and supporting next-generation technology demands.
This workshop underscored SHINE’s commitment to bringing industry leaders to discuss pressing topics in semiconductor innovation and development. We extend our gratitude to Dr. Rao for his thought-provoking presentation and look forward to future sessions in this impactful speaker series.
