Publication

For system-technology co-design (STCO) of BEOL compatible beyond-Silicon heterogeneously integrated (Oxide & 2D material) materials, we investigated the monolithic 3D integration of vertically stacked 1T1R and 2T0C1R DRAM-RRAM hybrid memory array with IGZO FETs and MoS2 analog RRAMs for low voltage switching. Our wafer-scale process (<400∘C) demonstrates good device performance. The ITO-enhanced IGZO selecting transistors (Ion=196.5μA/μm,Ioff =1pA/μmatVd=1V) integrated with solution deposited MoS2 switching layer (3.6 nm), enable 1T1R memory cells with programming current <100μA and voltage <1V, compatible with CMOS logic core voltages.

Furthermore, to address RRAMs endurance limitations, we propose an ultra-compact vertically stacked 2T0C1R gain cell DRAM-RRAM hybrid using dual-gated IGZO FET. We also propose an all-IGZO buffer capable of 3D BEOL data pipelining for concurrent multi-stacked array operations. Such 3D analog compute-in-memory architecture significantly reduces ADC energy overheads, achieving 121 TOPS/W efficiency and 4.73 TOPS throughput.

Researcher/Author: 

Dr. Baoshan Tang, Dr. Zihang Fang, Dr. Ruyue Wan, Dr. Sonu Hooda, Dr. Jin Feng Leong, Dr. Quanzhen Wan, Dr ChunKuei Chen, Dr Evgeny Zamburg, Dr JoongSik Kim and Prof Aaron Thean

Published in: 2024 IEEE International Electron Devices Meeting (IEDM)

Added to IEEE Xplore, 18 Feb 2025

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DOI: 10.1109/IEDM50854.2024.10873575