Publication

Modern integrated circuit design often involves integrating multiple smaller, specialized dies (often called chiplets or tiles) into a single package. This approach, known as chiplet-based integration or 3D integration [1], enables the creation of complex, high-performance, and cost-effective systems. Heterogeneously integrated systems based on chiplets invariably require an extra testing/screening step for individual chiplets before integration and full-system testing. This creates a fundamental challenge in ultra-low power (∼μW) and low cost systems (few tens of cents) for the loT, whose total testing budget is generally limited to a few cents. Hence, innovation at the boundary of testing equipment and chiplets is needed to significantly reduce chiplet testing cost over traditional testing approaches.

Researcher/Author: 

Neelkamal Semwal, Luigi Fassio, Massimo Alioto

Published in:  

2025 IEEE Custom Integrated Circuits Conference (CICC)

Date of Conference: 13-17 April 2025

Date Added to IEEE Xplore: 19 May 2025 

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DOI:  

https://ieeexplore.ieee.org/document/10983320