Publication

In this article, a novel architecture to detect laser voltage probing (LVP) attacks is introduced to make silicon systems secure against such threats, while pushing the area overhead to a level that is compatible with low-cost chip products. The inherent and sharp temperature rise due to the presence of a laser beam (i.e., an attack) is detected by sensing the resulting exponential leakage increase. In turn, this is achieved by sensing the leakage of the logic under protection via intermittent power gating, suppressing altogether area-hungry and explicit sensors in prior art. In particular, the rate of the virtual supply decay rate is sensed via simple and local voltage comparison. The proposed approach is seamlessly incorporated into an automated digital design flow, and the inherent resilience against process/voltage/temperature variations suppresses any postsilicon calibration. Extensive LVP attacks on a 28 nm testchip demonstrate attack decision margin well above six standard deviations, insignificant power overhead, percentage point-range performance degradation, and 4.35% area overhead ( 13.3× better than prior best). This enables for the first time ubiquitous inclusion of LVP protection even in low-cost consumer electronics.

Researcher/Author: 

Lead Co-Investigator –  Prof Massimo Alioto

Researchers – Hui Zhang,  Longyang Lin, Dingyi Xiong

Published in:  

 IEEE Journal of Solid-State Circuits

Date Added : 19 September 2025 

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DOI:  

https://ieeexplore.ieee.org/document/11173930