Publication
- One-Wire Architecture for Chiplet Reuse and Integration in Low-Dimensional Systems
A one-wire heterogeneous system architecture integrates self-powered chiplets with minimal inter-chiplet supply/data/timing distribution complexity for low-dimensional, routing-constrained systems. The hub chiplet manages supply via event-driven voltage regulation and uses voltage-mode ASK and current-mode ASK for downstream and upstream communication, respectively. The current-mode signal is recovered from the inevitable supply noise via a wireline wake-up receiver scheme. All functions are demonstrated in a self-contained system-on-a-wire for body monitoring, showing 48.5-nW average power in 180 nm.
Researcher/Author:
Lead Co-Investigator – Prof Massimo Alioto
Researchers – Anil Kumar Gundu, Neelkamal Semwal
Published in:
IEEE Xplore
Date Added : 13 May 2026
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DOI: