The Asian Deans’ Forum 2024 – The Rising Stars Women in Engineering Workshop, organized by Asia’s top engineering institutions and hosted by the National University of Singapore, aims to unite young women professionals in engineering from around the globe. This workshop fosters collaboration among scholars, researchers, and engineers pursuing academic careers, while serving as a platform for scientific and career-focused discussions that empower women academic leaders in Asia.

Dr. David Xu, Process Engineering Research Lead, kicked off the visit with an engaging overview of SHINE and E6NanoFab’s capabilities.  Participants explored our cleanrooms of varying classifications and dry labs, gaining insights into cutting-edge technologies in deposition, lithography, metrology, characterization, and packaging.

We extend our deepest gratitude to the dedicated team of researchers, engineers, and laboratory officers at the Packaging Facilities @ SHINE Centre and E6NanoFab for their exceptional efforts in making the tour a resounding success.

1. Energy and Processing Challenges: Approximately 50% of power in these systems is dissipated by compute chips, an area that Moore’s Law alone cannot continue to address. Advanced packaging and photonics are essential to handle the high energy demands and data movement challenges between compute and memory chips. Dr. Rao proposed developing innovative approaches for monolithic 3D post-processing and advanced packaging solutions to meet these demands.
2. Technological Innovations Enabling Moore’s Law Scaling: Dr. Rao emphasized that many advanced technologies, including EUV, nanoimprint, multi-patterning, and monolithic 3D, are crucial for scaling Moore’s Law through 2037 and beyond. New developments in multi e-beam mask writers with 500K beams, as well as computers optimized for advanced lithography, are paving the way for these innovations.
3. Stacked Nanosheet Transistors and Defect Management: Stacked nanosheet transistors are expected to be the workhorse for future chip designs. Dr. Rao discussed the importance of integrating these new device concepts with advanced packaging methods such as Stanford’s N3XT 3D Mosaic. Furthermore, he highlighted that addressing defect, yield, reliability, and metrology issues is essential to sustaining Moore’s Law, as these factors will impact the feasibility of next-generation semiconductor technologies.
4. Cooled CMOS and Heterogeneous Integration: Cooled CMOS presents a promising opportunity, provided effective thermal solutions can be developed. Heterogeneous integration and the use of chiplets enable higher yields and reduced costs by interconnecting smaller die on a single substrate. This integration also allows for the inclusion of novel devices that are otherwise difficult to incorporate directly onto silicon.

Dr. Chuei-Tang Wang (CT Wang) shared his experiences, noting that his first visit to Singapore was over 15 years ago and this was his third visit. Since joining TSMC in 2022, Dr. Wang has been involved in the packaging research works. Some of his significant contributions include 170 US patents and 35 papers in prestigious conferences such as VLSI, IEDM, and ECTC. Dr. CT Wang announced that TSMC would sponsor two projects: the Advanced Freeform Optical Waveguide, led by Prof. Yeow Kheng Lim, SHINE Programme Director, and the Thermal Management Solution for High-power Wafer, led by Prof. Aaron Thean, SHINE Director, with Assistant Prof. Sunmi Shin of the NUS Mechanical Engineering Department as Co-investigator. He emphasized the importance of low power consumption chips and optical computing in the AI era, highlighting these as critical research areas.

enable acad-industry co-research sandbox, and incubate small-semi spin-offs and talent creation and development. He introduced SHINE’s shared facilities to spur capabilities akin to some of the industry’s standards and its diversity of talents. He reiterated the alignment of SHINE with the latest launch by Nvidia, bringing a new Era with exciting new opportunities going beyond Moore’s law.