Stretchable hybrid devices have enabled high-fidelity implantable and on-skin monitoring of physiological signals. These devices typically contain soft modules that match the mechanical requirements in humans and soft robots, rigid modules containing Si-based microelectronics and protective encapsulation modules. To make such a system mechanically compliant, the interconnects between the modules need to tolerate stress concentration that may limit their stretching and ultimately cause debonding failure. Here, we report a universal interface that can reliably connect soft, rigid and encapsulation modules together to form robust and highly stretchable devices in a plug-and-play manner. The interface, consisting of interpenetrating polymer and metal nanostructures, connects modules by simply pressing without using pastes. Its formation is depicted by a biphasic network growth model. Soft–soft modules joined by this interface achieved 600% and 180% mechanical and electrical stretchability, respectively. Soft and rigid modules can also be electrically connected using the above interface. Encapsulation on soft modules with this interface is strongly adhesive with an interfacial toughness of 0.24 N mm−1. As a proof of concept, we use this interface to assemble stretchable devices for in vivo neuromodulation and on-skin electromyography, with high signal quality and mechanical resistance. We expect such a plug-and-play interface to simplify and accelerate the development of on-skin and implantable stretchable devices.

Researcher/Author: Ying Jiang (NTU), Shaobo Ji (NUS), Jing Sun (SIAT/CAS), Jianping Huang (SIAT/CAS), Yuanheng Li, Guijin Zou (A*STAR IHPC), Teddy Salim (NTU), Changxian Wang (NTU), Wenlong Li (A*STAR IME), Haoran Jin (NTU/NUS), Jie Xu (Standford), Sihong Wang (Stanford), Ting Lei (Standford), Xuzhou Yan (Stanford), Wendy Yen Xian Peh (NUS), Shih-Cheng Yen (NUS), Zhihua Liu (NUS), Mei Yu (SIAT/CAS), Hang Zhao (SIAT/CAS), Zechao Lu (SIAT/CAS), Guanglin Li (SIAT/CAS), Huajian Gao (A*STAR IHPC), Zhiyuan Liu (SIAT/CAS), Zhenan Bao (Standford) & Xiaodong Chen (NTU)

Nature volume 614, pages456–462 (2023)
https://www.nature.com/articles/s41586-022-05579-z

In this article, we demonstrate a low-thermal budget defect-engineered process to achieve top-gated (TG) oxide–semiconductor ferroelectric field-effect transistors (FeFETs). The demonstrated TG FeFETs, with the channel length scaled down to 40 nm, exhibit a highly stabilized ferroelectric memory window (MW) of 2 V and a high current ON/OFF ratio of 106. This is achieved by an engineered InGaZnOx (IGZO) and InSnOx (ITO) heterojunction channel that produces the defect self-compensation effect to passivate the intrinsic oxygen-deficient defects, existing in the indium-gallium-zinc-oxide (IGZO) channel interface and bulk. Effective interface/bulk defects passivation with good control of defect-induced channel carrier concentration has been notoriously difficult to achieve. Hence, realizing performant TG oxide-based FeFETs with back-end-of-line (BEOL) thermal budget constraints remains a fundamental challenge. Our study shows that heterojunction channel engineering on FETs and FeFETs can be a reliable solution to overcome this challenge. With such a technique, we can now enable double-gated (DG) ITO–IGZO FeFET and FETs. Such devices can enable BEOL-compatible reconfigurable nonvolatile logic switches that provide extremely low off-state leakage, high switch conductance ratio, and memory read-write disturb-free features.

Researcher/Author:
Aaron Voon-Yew Thean, Chun-Kuei Chen, Sonu Hooda, Zihang Fang, Manohar Lal, Zefeng Xu, Jieming Pan, Shih-Hao Tsai, and Evgeny Zamburg 

Published in: IEEE Transactions on Electron Devices ( Volume: 70, Issue: 4, April 2023) International Electron Devices Meeting (IEDM)
Page(s):  2098 – 2105

https://ieeexplore.ieee.org/document/10043682

If Si CMOS for massive M3D is difficult due to need for high-thermal-budget processes, are there solutions that are beyond Si? In this article, we discuss two low-thermal budget approaches: Oxide Semiconductor and 2D Materials for M3D integration. By reviewing some of our recent work with IGZO-based transistors and memories, followed by our investigation of the 2D material opportunities for 3D memories, we highlight the need for new low-thermal-budget additive techniques for heterogenous multi-material integration as well as low-temperature material modification. Given the unlikelihood of “perfect materials”, new system architecture-material-device co-design intervention will be essential to capitalize on the specific trade-offs of the components.

Researcher/Author: 
Aaron Voon-Yew Thean^†, Evgeny Zamburg^†, Shih-Hao Tsai, Chun-Kuei Chen, Maheswari Sivan, Baoshan Tang, Sonu Hooda, Zihang Fang, Jieming Pan, Jinfeng Leong, and Hasita Veluri. 

Published in: 2022 International Electron Devices Meeting (IEDM)

https://ieeexplore.ieee.org/document/10019501

We demonstrate, for the first time, a short-channel (L G :40nm) back-end-of-line (BEOL) compatible top-gated (TG) self-aligned FeFETs with the ultra-low interface/bulk trap density (D it /D bulk ) down to 10 ¹¹ cm ^-2 eV ^-1 , a 100x improvement over conventional amorphous Indium-Gallium-Zinc-Oxide (IGZO) devices. High memory and drive performance are both achieved, exhibiting a large and stable memory window of 2.1V, excellent endurance exceeding 10 ⁷ cycles, close-to-ideal subthreshold swing (S.S.) of 62mV/dec., and the record-low read-after-write delay of 200ns. This is accomplished by utilizing the defect self-compensation effect in the ITO-IGZO heterojunction channels for ferroelectric top-gate stack stabilization. We leverage these advantages and proposed a novel Monolithic 3D (M3D) FPGA architecture with the demonstrated short-channel (L G :40nm) BEOL dual-gated (DG) merged memory-logic FeFETs with excellent drive performance as a non-volatile reconfigurable interconnect switch. Our BEOL-compatible DG FeFET switch enables a compact interconnect switch fabrics with a V/2 bias scheme, featuring excellent G on /G off of 10 ⁶ , ultra-low sub-pA leakage, disturb-free, and sneak-current-free read-write operation. This work sets new oxide-semiconductor FeFET performance records useful for future BEOL nonvolatile logic applications.

Researcher/Author from Department of Electrical and Computer Engineering: 
Aaron Voon-Yew Thean; Evgeny Zamburg; Chun-Kuei Chen; Zihang Fang; Sonu Hooda; Manohar Lal; Umesh Chand; Zefeng Xu; Jieming Pan; Shih-Hao Tsai

Published in: 2022 International Electron Devices Meeting (IEDM)

https://ieeexplore.ieee.org/document/10019440